1. Field of the Invention
The present invention relates to a regulator and a related control method, and more particularly, to a regulator and a related control method for preventing exceeding initial current by a secondary current of an additional current mirror.
2. Description of the Prior Art
Currently, microcontrollers are essential to electronic products such as cellular phones, computers, and servers. How to make microcontrollers operate effectively becomes one of the most important topics to researchers and developers.
In order to optimize the volume density of elements, the power consumption and the operation speed of microcontroller semiconductor circuits, the driving voltage of the core circuit in the chip and the voltage of the corresponding signal are usually lower than those of common circuits. Hence, an I/O buffer for signal translation between different voltages is needed. FIG. 1 is a block diagram of a conventional chip 10 and a related circuit board 12. For example, the circuit board 12 is a motherboard of a personal computer and the chip 10 is a related controlling chip such as North/South Bridge Chip. In another example, the circuit board 12 is an add-on card such as an Ethernet Card and the chip 10 is a related controlling chip. The chip 10 contains a core circuit 14 and an I/O circuit 16. Processed signals from the core circuit 14 to the circuit board 12 or signals to be processed from the circuit board 12 to the core circuit 14 should go through the I/O circuit 16 where the signals are buffered and transformed. As mentioned before, the core circuit 14 is biased by a lower voltage and the voltage of all the processed signals are lower than that of the circuit board 12. In order to transmit the signals from the core circuit 14 to the circuit board 12, the circuit 16 increases the voltage and the power of the related signals. In order to transmit the signals from the circuit board 12 to the core circuit 14, the circuit 16 decreases the voltage and the power of the related signals.
As the I/O circuit 16 and the circuit board 12 are designed to exchange data directly, they are usually biased by the same voltage. In FIG. 1 the DC voltage Vcc, Vss (Vss is typically ground voltage) are applied for biasing the circuit board 12 and the core circuit 16 in the chip 10. As mentioned before, the core circuit is biased by a lower voltage and the chip 10 should include a regulator 18 in order to provide a regulated voltage Vp25 for biasing the core circuit 14. Typically, the circuit board 12 can provide a DC voltage of 3.3V for the chip 10 and the core circuit 14 is biased by a lower voltage 2.5V. In such a case, the regulator should utilize the DC voltage of 3.3V to produce the DC voltage of 2.5V in order to meet the electrical requirement of the core circuit 14. In the chip 10 there is a detection circuit 26 electrically connected with the node Np0 that checks if the regulated voltage is generated and sends a detection signal Vpg0 to indicate the detection result.
As FIG. 1 shows, conventionally the regulator 18 utilizes a pnp-type bipolar junction transistor Qp1 on the circuit board 12 for circuit charging and a capacitive module 24 containing a capacitor Cp1 of high capacitance on the circuit board 12 and a capacitor Cp2 for bypassing. Adapting to the transistor Qp1 and the capacitive module 24 on the circuit board 12, the chip 10 contains an operational amplifier 20, a band-gap circuit 22, and a voltage divider including two resistors Rp0, Rp1. The regulator 18 is biased by the DC voltage difference between Vcc and Vss. The band-gap circuit 22 provides a reference voltage Vbg0. The operational amplifier 20 has differential input ends Inn0, Inp0 electrically connected with the node Np1 and the band-gap circuit 22 individually, and its output end Op0 is connected with the base of the transistor Qp1 to control the driving voltage Vd0 and the driving current Ib0. The chip 10 may have a pin as the connection between the output Op0 and the transistor Qp1 on the circuit board 12. The emitter of the transistor Qp1 is biased at the DC voltage Vcc and the node Np0 is electrically connected with the capacitive module 24. The capacitive module 24 has a capacitor Cp1 of high capacitance to regulate its output voltage and a capacitor Cp2 for bypassing AC interference. When the capacitor is charged and reaches a steady state, a regulated voltage Vp25 is established at the node Np0. The regulated voltage Vp25 of the capacitive module 24 at the node Np0 is applied back to the chip 10 via another pin. The regulated voltage Vp25 is applied to the core circuit 14 as a DC bias voltage; meanwhile, at the node Np1 a divided voltage Vs0 is established via the voltage divider, the resistors Rp0, Rp1. The operational amplifier 20 compares the reference voltage Vbg0 with the voltage Vs0, and then sends a feedback signal to the transistor Qp1 to control the driving voltage Vd0 and the driving current Id0. Moreover, while the chip 10 is not operated, the circuit board 12 need not to provide the DC voltage Vcc for biasing the chip 10 and the regulator 18 is idle. Hence, the voltage of the node Np0 is equivalent to the lower DC voltage Vss.
The following relates the operation of the regulator 18. The circuit board 12 enables the chip 10 with the DC voltage Vcc applied to the regulator 18. The band-gap circuit 22 and the operational amplifier 20 start functioning and the operational amplifier 20 starts to compare Vs0, the voltage of Np1, with Vbg0, the reference voltage generated by the band-gap circuit. As the voltage of the node Np0 and the voltage Vs0 stay low before the regulator 18 starts functioning, the voltage Vd0 of the output end Op0 of the operational amplifier 20 correspondingly stays low due to the fact that the voltage Vs0 is much smaller than the reference voltage Vbg0 when the operational amplifier 20 starts functioning. The voltage difference between the emitter and the base of the transistor Qp1 is almost the same as the voltage difference between the DC voltages Vcc, Vss. And, the operational amplifier 20 functions as a current sink obtaining driving current Ib0 from the base of the transistor Qp1 to drive it, enabling the large current Ic0 between the emitter and the collector to affect the capacitive module 24, such as to charge the high capacitance capacitor Cp1 in the capacitive module 24. As known by those skilled in the art, through the current driving characteristic of the bipolar junction transistor and the driving current Ib0 obtained from the base of the transistor Qp1 by the operational amplifier 20, the operational amplifier 20 can drive and control the current Ic0 between the emitter and the collector of the transistor Qp1 according to Ic0=β*Ib0, where β is the current magnification of the bipolar junction transistor.
As the charging process continues, the voltage of the node Np0 increases, and Vs0, the voltage of the node Np1, increases gradually. Correspondingly at the output Op0 of the operational amplifier 20, the driving voltage Vd0 increases and the driving current Ib0 decreases so that the voltage difference between the emitter and the base of the transistor Qp1 decreases with a low degree of turning on, and the current Ic0 decreases gradually. Through the feedback of the voltage Vs0, the operational amplifier 20 can control the driving voltage Vd0 and the voltage Vp25 at the node Np0 will approach a constant value of a steady state. When the steady state approaches, the operational amplifier 20 makes the voltage Vs0 equivalent to the reference voltage Vbg0. That is, the voltage Vp25 equals (1+Rp0/Rp1)Vbg0. The regulated voltage Vp25 may be applied to the core circuit 14 to bias it, and the current Ic1, which the core circuit 14 needs while operating, is supplied by the transistor Qp1. When the voltage V25 fluctuates, the operational amplifier 20 will correspondingly control the driving voltage Vd0 and the driving current Ib0 for dynamic compensation. For example, if the current loading of the core circuit 14 increases for a large amount of calculation, the capacitor Cp1 will prevent the voltage Vp25 at the node Np0 from decreasing rapidly. In addition, the voltage decrease of Vs0, the decrease of the driving voltage Vd0, the increase of the voltage between the emitter and the base of the transistor Qp1 are induced correspondingly for the slight voltage decrease of Vp25 so that the current Ic0 of the transistor Qp1 is increased to meet the requirement of the core circuit 14. Besides, as mentioned above, the chip 10 has the detection circuit 26 to detect if the regulated voltage Vp25 is established normally. In this establishing process, when the regulated voltage Vp25 of the regulator 18 just increases gradually from a low level, the voltage Vgp0 generated by the detection circuit 26 stays at a low level representing a digital “0” meaning that the regulated voltage Vp25 has not been established. When the regulated voltage Vp25 reach a predetermined voltage, (e.g. 90% of the regulated voltage in the steady state), the voltage Vgp0 generated by the detection circuit 26 switches to a high level representing a digital “1” meaning that the regulated voltage Vp25 has been established, i.e. power-good. The I/O circuit 16 and the core circuit 14 shall cooperate to make the chip 10 functional, but the I/O circuit 16 is biased at the voltage Vcc prior to the establishment of the regulated voltage Vp25 for biasing the core circuit 14. In order to coordinate, the I/O circuit 15 and the core circuit 14 will reset at the same time when the digital “1” of the voltage Vgp0 of the detection circuit 26 is generated.
Please refer to FIG. 2 illustrating the function of the operational amplifier 20 of FIG. 1 during the establishment of the regulated voltage Vp25. The operational amplifier 20, which is biased by the voltage difference between Vcc and Vss, comprises NMOS transistors M1˜M8 and PMOS transistors M9˜M14 to form an amplifying circuit 29 and a driving stage 28 of class AB output. The driving stage 28 is formed with transistors M8, M14 and the amplifying circuit 29 is formed with the other transistors. The substrates of NMOS transistors M1˜M8 are biased at Vss and those of PMOS transistors M9˜M14 are biased at Vcc. The transistors M1, M2 form a differential pair and having gates forming the input ends Inp0, Inn0 respectively. The gates of the transistors M3˜M6 are electrically connected forming a current mirror, through which a support circuit 27 providing a reference current Ir0 can apply the bias to the amplifying circuit 29. For example, the transistor M4 electrically connected with the node Np3 is the current source to bias the differential pair formed with the transistors M1, M2. To summarize, the transistors M1, M2, M9, M10 functioning as differential pairs send the signals to the transistors M7, M3, M12, M13 functioning as the buffer. The output voltages of the amplifying circuit 29 at the nodes Np5, Np6 will individually control the gate voltages of the transistors M8, M14 of the driving stage 28, of which the node Np4 is the output end Op0 of the operational amplifier 20, referring back to FIG. 1.
As mentioned above, conventionally when the regulator 18 start functioning, it will obtain a certain amount of current Ib0 from the base of the transistor Qp1 to turn on the large charging current Ic0 of the transistor Qp1, as shown in FIG. 1.
In FIG. 2 the circuit diagram shows the conventional structure of the operational amplifier 20. When the regulator 18 starts functioning, the regulated voltage Vp25 of the node Np0, referring to FIG. 1, is almost the same as the DC voltage Vss, which is of a lower level, so the divided voltage Vs0 at the node Np1 is also of a lower level, and consequently, so is that of the input end Inp0 of the operational amplifier 20. Compared with the reference voltage Vbg0 (typically between 1˜2 Volts) of a higher level at the input end Inn0, the voltage of a lower level at the input end Inp0 nearly turns off the transistor M1 as shown in FIG. 2. The current provided by the transistor M4 is mainly conducted by the transistor M2 so the gate voltage of the transistor M7 is pulled to a voltage Vcc of a high level and the voltages at the node Np5, Np6 are consequently pulled high. Such situation turns off the transistor M14 and makes the current Id0 of the transistor M8 high, the current Id0 being the driving current Ib0 obtained from the base of the transistor Qp1 by the operational amplifier 20 via its input end Op. Then, the driving current Ib0 will turn on the transistor Qp1 to provide the large charging current Ic0. That is, the base of the transistor Qp1 is regarded as a control end and the node Np4 is regarded as a control node, through which the driving current Ib0 determines the driving status of the transistor Qp1. The degree of current flowing between the drain and the source of the transistor M8 determines the current flowing from the node Np4 and consequently controls the charging current Ic0 provided by the transistor Qp1.
Conventionally, the regulator 18 in FIG. 1 can generate the regulated voltage Vp25 to bias the core circuit 14. Of concern is the regulator 18 initially overdriving the transistor Qp1 and burning it out due to an overly large current. As mentioned above, when the regulator 18 start functioning, the low voltage at the node Np0 makes the driving voltage Vd0 low at the output end Op0 of the operational amplifier 20. Accordingly the voltage difference between the emitter and the base of the transistor Qp1 is almost the same as that between DC voltages Vcc, Vss, and the NMOS transistor M8 of the driving stage 28 of the operational amplifier 20 turns on the driving current Ib0 driving the transistor Qp1 and turns on the large current Ic0 in the transistor Qp1. According to the typical case mentioned above, the voltage difference between DC voltages Vcc, Vss is 3.3 Volts, but the voltage difference needed for operation between the emitter and the base of the transistor Qp1 is only 0.7˜0.8 Volts. As a result, the initial turned-on current of the transistor Qp1 is much larger than what is needed in normal operation. Such a large current burns the transistor Qp1 out in the beginning of the operation of the regulator 18. Therefore, the regulator 18 cannot function well to provide the regulated voltage Vp25 to bias the chip 10, and the microcontroller fails to function.